VLSI Circuits for Cryptographic Authentication

Nowadays, digital communication protocols rely on cryptographic mechanisms to protect sensitive information from unauthorized access and modification. Cryptographic primitives, such as hash functions, block and stream ciphers, are key components of many information security applications, employed to provide privacy, authentication, and data integrity. Following the massive differentiation of modern communication technologies, cryptography must be able to provide highlyefficient algorithms that combine strong security with optimal implementability. It becomes therefore unlikely that a single cipher or hash function would be able to meet all the constraints imposed by the wide plethora of communication protocols. Researchers and designers are thus asked to develop application-specific algorithms that are jointly optimized for security and implementation performance. This thesis is concerned with the design of very large scale integration (VLSI) circuits for cryptographic hash functions and block cipher authenticated encryption modes. We present two hash algorithms that have been submitted to the public hash competition organized by the U.S. National Institute of Standards and Technology (NIST). A complete design space exploration of their efficiency for application-specific integrated circuits (ASICs) is given. Due to our strong involvement in the competition, we further developed a uniform methodology for a fair comparison of the VLSI performance of the second round candidate algorithms. Our benchmarking framework is the result of three different research projects that culminated with the fabrication of three 0.18 μm and 90 nm ASICs, hosting the second round function cores. In the second part of this thesis, we investigate high-speed fieldprogrammable gate array (FPGA) designs of the Advanced Encryption Standard (AES) in the Galois/Counter Mode (GCM) of operation